Research on RISC-V-based Edge Convolution Acceleration Extension Instruction Set

Leveraging the scalability mechanisms of the RISCV instruction set architecture, this study designed and implemented five Single Instruction Multiple Data (SIMD) custom instructions to systematically optimize key computational stages in Convolutional Neural Networks (CNNs), including convolution operations, activation functions, and pooling. By refining data locality access strategies, the proposed solution reduces memory access cycles from 64 benchmark cycles to 36 cycles in a representative $6 \times 6$ input feature map scenario (stride=2, padding $=0$), while only requiring the extension of four temporary matrix registers. The custom instructions were integrated with C language code via an inline assembly abstraction layer, enabling collaborative compilation. The full architecture underwent hardware prototyping on a modified Hummingbirdv2 E203 processor core and was functionally validated on an FPGA-based hardware verification platform.