Design and Implementation of a NoC Router for Programmable System-on-Chip Platforms

With the continuous advancement of semiconductor processes and the ever-increasing demand for high-performance computing, the number of integrated IP cores and high-speed interfaces in Programmable System-on-Chip (PSoC) platforms has surged, rendering on-chip data transmission a critical performance bottleneck. To overcome this limitation, Network-on-Chip (NoC)—a packet-switched, chip-level interconnection architecture—has emerged, with the router as its core component. This paper designs and implements an efficient NoC router for PSoC based on Verilog. At the routing level, a hop-count-based adaptive XY algorithm is employed to dynamically circumvent network congestion. At the flow-control level, a QoS-priority-based arbitration scheme and buffer reorganization mechanism are designed to guarantee the timely transmission of high-priority transactions. ModelSim 10.5 simulation results demonstrate that, under various traffic scenarios, the proposed router significantly reduces transmission latency, alleviates network congestion, and effectively ensures the quality of service for critical data.