Low Complexity Three’s Complement Parallel Multiplier Using Special Operators of Ternary Logic

Arithmetic units in multivalued logic have been extensively researched in the last decade in the context of emerging nanodevices. While considerable work has been done on adder and multiplier designs, the focus has been on handling unsigned numbers. In this brief, we first present an algorithm for multiplication of a pair of signed ternary numbers represented in three’s complement format. The algorithm leads to partial product digits which are all positive. Using a special class of operators in ternary logic, we then present a hardware-efficient realization of the algorithm that leads to low multiplexer count. The special operators also contribute to power reduction. Technology assessment using Carbon Nanotube FET (CNTFET) reveals that the proposed multiplier achieves substantial reduction in power-delay product (PDP) over the best existing design. In particular, the savings in PDP for 6 × 6 and 36 × 36 multipliers are 32% and 38% respectively.