The Impact of Power Module Layout on Stray Inductance

With the rapid development of power electronics technology, SiC power modules are increasingly being used in various electric vehicles. The performance of SiC power modules directly affects the efficiency and reliability of the entire system. Stray inductance, as an important parasitic parameter in power modules, has a significant impact on the module's switching characteristics, electromagnetic compatibility, and overall performance. The layout design of power modules is one of the key factors affecting stray inductance. SiC devices are more sensitive to module stray inductance, and to achieve parallel operation of multiple chips, it is necessary to minimize stray inductance as much as possible. Optimizing the layout can effectively reduce stray inductance, optimize gate waveforms, and improve module performance. This paper analyzes and compares the stray inductance of modules under different layout structures through simulation, and compares the impact of different layouts on stray inductance. The optimized scheme is then tested through packaging, ultimately seeking the optimal layout.