Area-Adjusted Comparison of BSPDN Interconnects in CFET: Superiority of Frontside Connection

The complementary field-effect transistors (CFETs) are promising for next-generation logic devices, but tall vias (TVs) face challenges, including high resistance, parasitic capacitance, and metal void defects. This study evaluates three source-side to backside power delivery network (BSPDN) interconnect structures: conventional TV, line-type TV (LTV), and frontside connection (FSC). FSC utilizes frontside metal lines with power tap cells (PTCs) for front-to-back connectivity, offering a scalable solution. Through 3D-TCAD simulations, we analyze their cell-level and area-adjusted performance. FSC achieves a + 2.2% higher frequency at the same power (Freq. at $P$ ) and a −4.7% lower power at the same frequency (Power at F) compared to TV, while maintaining consistent performance across cell height (CH) scaling. In contrast, TV and LTV exhibit degradation due to increased resistance and capacitance at reduced CH. FSC’s sweet zone (12–71 CPPs) ensures sufficient margin for PTC insertion, delivering a 1.7% Freq. at $P$ gain at 31 CPPs and 12% area reduction at zero frequency offset. Notably, FSC’s compatibility with nonvertical via profiles (essential for void prevention) further enhances its advantages in real processes. These results demonstrate FSC’s superior power, performance, and area (PPA) characteristics, positioning it as a robust alternative to TV/LTV for CFET architectures. The study provides critical insights for advancing the next-generation logic devices.