A 12-bit 320MS/s Current-steering DAC With 70dBc SFDR in 22nm CMOS

A 12-bit 320MS/s current-steering digital-to-analog converter (DAC) is designed in a 22-nm CMOS process. A twostage cascode current source structure was employed to enhance the finite output impedance, and two constant branch currents were added to further improve the linearity of the output. In this design, a common-centroid four-quadrant layout was adopted. Post-simulation results in 22-nm CMOS show that for an input signal up to 138MHz, the SFDR and the SNR of the presented 320MS/s DAC achieve 70dB and 71dB respectively, with a maximum output current of 2mA. The DAC consumes 3.293mW of power with supply voltages of 0.9V and 2.5V, and the chip area is 0.074mm².