An Adaptive Digital Loop Filter for Fast-Locking TDC-Based ADPLL

An adaptive digital loop filter (DLF) for fast-locking TDC-based all-digital phase-locked loop (ADPLL) is proposed. The proposed DLF utilizes a proportional-integral filter structure with dynamically adjustable integral coefficients, which is controlled by a finite state machine (FSM). The adaptive method optimizes the response speed and stability according to the magnitude of the phase error and its variation. An adaptive DLF based ADPLL is implemented in 130 nm SiGe BiCMOS technology. The simulation result shows that the proposed ADPLL with adaptive DLF can achieve a locking time of $2.46 \mu s$ at 3.5 GHz output frequency.