CNN Accelerator For Edge Inference

Deploying AI models on edge devices has become increasingly important due to the demand for low-latency and energy-efficient inference, especially in scenarios where real-time decision-making is critical. This work presents a Convolutional Neural Network (CNN) accelerator designed and optimized for edge inference using Vivado High-Level Synthesis (HLS) and deployed on a PYNQ FPGA board. The proposed design incorporates several HLS optimization directives such as PIPELINE and UNROLL to improve parallelism and reduce computation latency. Additionally, on-chip memory is efficiently managed using BLOCK storage pragmas, ensuring minimal off-chip memory access and enhanced data reuse. The LeNet5 CNN model used is tailored for image classification tasks, and its hardware implementation has been profiled for performance, resource utilization, and power efficiency. The accelerator achieves a 7.84x speedup in inference time compared to a software-based implementation running on a general-purpose processor. By leveraging FPGA’s reconfigurable nature and the HLS toolchain, the design demonstrates significant improvements in throughput, latency, and energy efficiency, making it well-suited for edge environments such as surveillance systems, IoT endpoints, and mobile robotics.