A Low-Power Neural Translation Accelerator: Hardware Architecture Design on Heterogeneous Computing Platforms

With the widespread application of the neural machine translation (NMT) models in the field of multilingual semantic understanding, its dependence on computing resources and power consumption has become a major challenge for deployment on resource-constrained edge devices. Therefore, this study proposes a neural translation accelerator hardware architecture for low-power deployment. At the same time, combined with the optimization strategy of heterogeneous computing platforms, the comprehensive performance of NMT models in translation accuracy, energy efficiency, and inference latency is systematically improved. First, this study introduces a neural translation method based on k-nearest neighbor retrieval enhancement at the algorithm level. This algorithm enhances semantic consistency and improves the BLEU index through contextual prompt mechanism and dynamic confidence control. Secondly, in terms of hardware architecture, a heterogeneous node system integrating ARMv8 CPU and multi-core DSP is constructed. At the same time, a multi-level parallel training and inference mechanism is designed, and DVFS energy consumption modeling, task scheduling state vector and migration priority function are introduced. This operation can achieve energy-efficiency-aware load balancing and system scheduling. Through experimental verification on embedded heterogeneous platforms, the architecture has demonstrated excellent performance in multiple dimensions. In terms of BLEU translation accuracy, it has been improved by up to 9.1% compared with traditional models; in terms of energy efficiency, BLEU/W has been improved to 8.82 per unit power consumption; system latency and average task waiting time have been reduced by 15.7% and 26.3% respectively. Experimental results show that the proposed architecture design and its scheduling mechanism can effectively support the low-power and efficient deployment of NMT models in edge computing scenarios.