Test Cycle Reduction for TSV Test Using Streaming Scan Network on 3-D IC

Through-silicon vias (TSVs) are essential for interdie connections in 3-D integrated circuits (3-D ICs), but their susceptibility to defects necessitates effective testing. As the correct operation of TSVs is critical to the overall reliability of 3-D ICs, their testing is regarded as an essential part of the 3-D IC testing process. Conventional TSV testing based on the IEEE-1838 standard architecture often increases test cycles due to the serial data application through die wrapper registers (DWRs). In this brief, an architecture is proposed that enables efficient TSV testing by using the streaming scan network (SSN) architecture, which is already utilized for logic core testing. TSV groups are treated as identical cores, allowing parallel application of test patterns via the SSN bus and streaming scan host (SSH). The experimental results show that the proposed method achieves a significant reduction in test cycles compared with the conventional TSV test method based on the IEEE-1838 standard architecture, without incurring a noticeable increase in area overhead. The reduction in test cycles becomes more pronounced as the number of TSVs increases.