Novel Multi-loop 3D-Interconnect-based Inductance Minimization Technique for Lateral WBG Device Power Modules

With the confluence of Wide Bandgap (WBG) power semiconductor device’s superior characteristics, trends of high efficiency, low volume and weight, and cost-effective solution for power electronics systems, the demands for the advanced power packaging are growing rapidly. Laterally conducting Gallium Nitride/Aluminum Gallium Nitride (GaN/AlGaN) heterojunction transistor is one of the WBG power devices and holds fast-switching characteristics enabling high efficiency and small form factor. To not limit the fast-switching advantages, an ultra-low inductance interconnection configuration for a half-bridge power module is proposed. This configuration includes an optimal power device orientation, package metalized trace layout, and a heterogeneously integrated power interposer (HIPI) using ultra-thin dielectrics. Ultra-low inductance is achieved by parallel-plate multi-loop interconnection which facilitates a significant magnetic field cancellation compared with the state-of-the-art single-loop structure.