Universal Stacked Die Layout Technique for Minimizing Parasitic Inductance in Flying Capacitor-based Multilevel Converters

Wide Bandgap (WBG) devices like Gallium Nitride (GaN) and Silicon Carbide (SiC) enhance power density in medium and high voltage applications due to their fast-switching speeds. Wire bondless (planar) technology is preferred for WBG device power module packaging, focusing on reducing parasitic inductances through optimized current commutation loop design, flip chip arrangement in double-sided cooled modules, clad organic dielectric and 3D Stacked Die packages. While current research, focuses on two-level single or multi-chip half-bridge power modules, interest in multilevel converters is rising in power electronics, though packaging hasn’t advanced similarly. Effective packaging for these converters is critical due to high parasitic inductance from series-connected devices in their commutation loops. This work introduces a novel layout technique using 3D Stacked Die packages with optimized High-Frequency current loops that can reduce power loop inductance in Flying Capacitor (FC)-based multilevel converters by up to 95%, significantly improving their performance.