Design and Analysis of a Source Parasitic Insensitive Fully-Passive N-Path Receiver With Sub-3 dB NF

This article presents an all-passive, source parasitic insensitive $N$ -path filter optimized for complex RF impedance matching. It works by nullifying the effect of the parasitic capacitance at the RF node through an additional nulling capacitor, which flips and cycles through adjacent phases and connects in parallel to the baseband (BB) capacitors during their respective on-phases. This effectively nullifies the charge on the capacitance at the RF node, and gives a design-freedom to reduce the “on”-resistance of the switches by increasing their sizes, thus leading to lower noise figure (NF) and better linearity. Matching is implemented by the appropriate choices of variable switched capacitor banks at the RF and the BB nodes. An analysis of the design procedure of the architecture is presented. The all-passive architecture was implemented in a standard 65 nm bulk-CMOS process and achieves a conversion gain between 1 and 3.5 dB, a NF between 2.6 and 3.5 dB, and in-band (IB) third-order intercept point (IIP3) and out-of-band (OOB)-IIP3 of + 19 and + 21 dBm, respectively, when the center frequency ( $f_{\text {LO}}$ ) was varied between 0.5 and 1GHz. The architecture consumes 12 mW of switching power at $f_{\text {LO}} =1$ GHz.