A Single-Channel 1–3 MASH SAR-Assisted Pipeline ADC With Residue Amplifier Error Shaping

This article presents a single-channel successive approximation register (SAR)-assisted fourth-order noise-shaping (NS) pipeline analog-to-digital converter (ADC) with residue amplifier (RA) error shaping. The first stage introduces a passive dynamic range (DR)-preserved feedforward (FF) NS, which shapes both the quantization error and various impairments from the RA, thus enabling a fast, low power, and voltage-and-temperature (VT) variation robust amplification. Further incorporating a coarse NS-SAR ADC to speed up the first-stage conversion, the critical path, formed by the quantization and amplification in the pipeline ADC, can be considerably shrunk, thus allowing for a high sampling rate. The second stage shares the error-shaped RA to achieve a second-order error feedback (EF) NS with optimized zeros, and simultaneously nests a simply passive first-order FF NS. These overall aggregate an aggressive fourth-order NS, achieving the desired SQNR under a low oversampling ratio (OSR), facilitating a low-power wideband design. Fabricated in 28-nm CMOS, the ADC prototype runs at a 760 MHz sampling rate and retains 100 MHz bandwidth (BW) with a signal-to-noise-and-distortion ratio (SNDR) of 70.15 dB under a small OSR of 3.8. It consumes 4.52 mW of power at a 1 V supply, yielding a Schreier figure-of-merit (FoM) of 173.6 dB. With a one-time-only trimming, the SNDR varies by 2 and 2.5 dB across a supply variation of ±10% and a temperature range of $- 20~^{\circ }$ C to $70~^{\circ }$ C, respectively.