Effect of Traps in Si/SiGe NPN Selectors for Cross-Point Memory Array Architecture

A latch-up bipolar junction transistor (BJT) selector device for memory crossbar architecture was fabricated using p⁺–Si ${}_{{1}-{x}}$ Ge _x as floating base sandwiched between n⁺-Si layers. The Ge concentration in the SiGe layers has varied between 25% and 40% and the base thickness between 25 and 35nm. The stack was etched with diameter of the device varied from 50 to 150nm. Finally, the devices were encapsulated using different materials. By using end of line (EOL) high-pressure (HP) H₂ annealing, the latch-up voltage ( ${V} _{\text {on}}\text {)}$ reduced from 2.75 to 2.2V (for 150-nm device diameter) and the nonlinearity (NL = ratio of currents at ${V} _{\text {on}} +100$ mV and that at the half of operating voltage) improved from $10^{{4}}$ to $3\times 10^{{4}}$ . This behavior was also studied by 1-D technology computer aided design (TCAD) simulation by introducing traps in the device. Traps at the floating base cause loss of hole, resulting in increased latch-up voltage and elevated leakage current. AlO _x and SiN _x offer superior passivation to deposited SiO₂, enhancing device performance. The device demonstrates excellent performance, achieving a low ${V} _{\text {on}}$ of 2.2 V, exceptional endurance exceeding $10^{{10}}$ cycles (under 0–3 V stress for 100 ns), and a high on-state current density of 14MA/cm² at 3 V. The results demonstrate the viability of the fabricated n-type/p-type/n-type (NPN) device as a high-endurance selector for crossbar memory architectures.