An E-band Broadband Transceiver for Integrated Sensing and Communication Applications in 65-nm CMOS

This paper presents a 71–86 GHz broadband transceiver for Integrated Sensing and Communication (ISAC) applications in 65-nm CMOS. To meet the demand of radar and communication for holistic local oscillator (LO) signal strategy, a low phase noise phase-locked loop (PLL), multipliers and a nested coupler with IQ calibration are designed to cover 76–81 GHz. The PLL can generate frequency modulated continuous wave (FMCW) chirp signal with a 5 GHz bandwidth and 4.93 MHz (0.1%) root-mean-square (RMS) frequency error at 300 MHz/us chirping rate, it can also support a fixed LO with a measured best phase noise (PN) of −97.21 dBc/Hz at 1 MHz offset at 76.8 GHz. In communication mode, the measured error vector magnitude (EVM) of the RX is less than -28.5 dB, and the EVM of TX is less than −29.2 dB in a 0.6 Gb/s 64-QAM signal. In radar mode, the transceiver can output signal with 5 GHz bandwidth and up to 300 MHz/us chirping rate. The proposed transceiver occupies a chip area of 3.4×3.4 mm² with power consumption of 550.8 mW.