A Ku-band Watt-Level 32-Way CMOS SOI Power Amplifier

This paper presents a 10–14.8 GHz 32-way hybrid-combined CMOS SOI power amplifier (PA), achieving 1.9-watt output power through a dual-grouped triple stack (DGTS) topology and a low-loss hybrid power combiner (HPC). The DGTS eliminates external gate capacitors via RF-grounded symmetrical stacking, enhancing voltage gain, output power, and tolerance to input imbalance. The HPC integrates four-way transformers, broadside-coupled transmission-line transformers, and T-line networks, reducing insertion loss while occupying a compact size. The experimental results verify a 3-dB bandwidth of 10–14.8 GHz, 32.8 dBm saturated output power (PSAT), and 24.3% peak power-added efficiency (PAE). Compared to state-of-the-art 8–18 GHz CMOS PAs, this work achieves the highest PSAT while maintaining competitive PAE, offering a scalable solution for 5G-Advanced/6G FR3 transmitters.