On the Design and Fabrication of PATH-based In-Memory Computing Multipliers

Processing in-memory is projected to reshape the computing landscape of accelerators for data-intensive applications. PATH-based computing is a promising in-memory computing paradigm for evaluating Boolean logic. Computation within the paradigm is performed by controlling the electrical flow of currents within 1 Transistor 1 ReRAM (1T1R) crossbar arrays using nonvolatile memory devices and access transistors. However, this paradigm has only been evaluated in simulation and needs to be verified in fabricated devices. In this paper, we propose an end-to-end framework for accelerating Boolean functions using PATH-based computing. The framework consists of a crossbar fabrication step, a logic synthesis step, and a circuit analysis step. The crossbar fabrication step involves fabricating 8x8 1T1R crossbar arrays using a 65 nm CMOS process. The second step maps the Boolean function into a crossbar design. The last step evaluates performance through crossbar testing and circuit simulation. The framework was evaluated with the fabricated crossbars using 2 and 3-bit multiplier designs. The experimental evaluation using both 8x8 arrays and Spice based simulation yielded similar results: 3-bit multiplier worked as designed while the 2-bit multiplier showed unexpected results. The resulting data will be useful to inform future logic designs for PATH-based computing.