A Low Power Pipelined Multilayered Vasanth Sorting for the elimination of Outliers in images

In order to remove outliers from Images, this work suggests a unique VLSI design for a four-level pipelined multi-layered Vasanth Sorting algorithm. Nine inputs are rankordered in ascending order using four layers of pipelining in the design. The concept is appropriate for real-time image processing applications because it makes use of pipelining and parallelism to achieve high throughput and low latency. Device used is Spartan-7 SP701 Evaluation Platform (xc7s100fgga6762). The suggested design strikes an excellent compromise between processing speed, space usage, and power consumption when compared to alternative sorting designs. From the conduction of verification of architecture, throughput of architecture is 12.8 MHz and it has been matched with theoretically expected output. The architecture consumes $43.75 \%$ less power compared to existing techniques. Hence an effective VLSI implementation for high-speed data sorting in real-time image processing applications is demonstrated.