System-level Power Integrity Enhancement Based on the Voltage Regulator Behavior Model for High-Performance Computing System

Ensuring system-level power integrity (PI) is a critical challenge in high-performance computing (HPC) systems as power demands continue to rise. The voltage regulator module (VRM) plays a key role in stable power delivery, and its interaction with the power delivery network (PDN) must be carefully considered to prevent voltage fluctuations. This paper presents a system-level PI analysis incorporating a VRM behavior model for HPC system. The study examines (1) the impact of PDN impedance on VRM design, (2) the role of VRM bandwidth in minimizing PDN impedance, and (3) the influence of VRM bandwidth on decoupling capacitor effectiveness. The results demonstrate that accounting for PDN impedance in VRM design helps prevent instability and enables optimal performance. Additionally, crossover frequency is a key factor in determining PDN impedance. Furthermore, when the frequency range dominated by the VRM overlaps with the effective range of decoupling capacitors, the impact of decaps is diminished. By considering this effect, increasing VRM bandwidth allows for an optimized design with fewer required decaps. These findings underscore the importance of VRM and PDN co-optimization in enhancing HPC system stability and efficiency.