Simulation Framework and Design Exploration of In-Situ Error Correction for Multi-Bit Computation-in-Memory Circuits

As computational complexity continues to increase, effectively designing a computation-in-memory (CIM) architecture has become a crucial task. In such an architecture, errors may occur due to factors such as voltage drift. This work focuses on designing a simulation framework for In-Situ error correction of multi-bit memory-in-computing circuits. The research concentrates on In-Situ error correction techniques, allowing the system to instantly detect and correct errors during memory or computational operations at the same location where data is being processed and stored. The primary goal of this work is to explore how to minimize the impact of these errors on model accuracy. In constructing the simulation environment, multi-bit weights are decomposed, and 2D convolutions are decomposed into matrix multiplications, then mapped onto the CIM architecture. Based on this framework, this work further analyzes hardware errors in CIM, including the causes of errors, statistical characteristics, and the impact of extreme error values on accuracy. Furthermore, we introduce and deeply analyze clamping as an error correction technique. Through a series of simulations, we came to the following clear conclusion: To maximize hardware efficiency and accuracy correction effects, special attention must be paid to high-bit weights and the protection of sensitive convolutional layers. In addition, reasonable setting of clamping threshold and appropriate array-based output grouping strategy are also indispensable. These strategies provide clear optimization directions for neural networks in specific application scenarios. After considering the above strategies and optimizing, the model accuracy can reach a maximum of 73.8%, which is close to the baseline of 75.8%. Considering that the protection circuit area is reduced by 50%, this result shows excellent benefits.