LogicCraft: LLM-Assisted Optimization of Netlist to Layout for Complex Custom Standard Cell Designs

In digital integrated circuit (IC) design, the need for custom standard cells tailored to specific design constraints, such as power, area, and performance, is increasingly critical. This paper presents an approach that leverages Large Language Models (LLMs) to automate the translation and optimization of Boolean tables into custom pull-up networks, using established principles to generate complementary pull-down networks. The proposed methodology focuses on automated translation, optimization, and seamless integration into standard electronic design automation (EDA) workflows. By utilizing LLMs, this approach significantly reduces design time, enhances optimization, and minimizes human error. This makes it a powerful tool for improving the efficiency and effectiveness of custom standard cell design in digital logic circuits.