A Reconfigurable Event Driven Accelerator for SNN Inference

Recent development in neuromorphic hardware focused on exploiting the temporal and spatial sparsity of Spiking Neural Networks (SNNs). Event driven accelerators have the benefit of lower latency and power compared to time-step driven architectures, but they are challenging to implement due to increased complexity of the neuron dynamics and irregular memory accesses. Here, we propose a scalable, flexible and customizable event-driven SNN accelerator designed for low latency and high capacity, with a hierarchical memory system and configurable neuron dynamics. The stateful nature of SNNs lead to frequent memory accesses, thus require a very high bandwidth to achieve a lower latency. While classic systolic array driven architectures opt for Static Random Access Memorys (SRAMs), SRAMs occupy a larger amount of area, limiting their capacity both on Application Specific ICs (ASICs) and Field Programmable Gate Arrays (FPGAs). In contrast, our accelerator leverages High Bandwidth Memory (HBM) as the main memory to achieve significantly higher capacity without sacrificing throughput. We benchmarked our accelerator on NMNIST and Spiking Heidelberg Digit (SHD) datasets. The system achieved 97.20% and 77.67% accuracy, respectively. Compared with state of the art implementations, our accelerator is able to process spike trains with very high time resolution, number of time-steps and little loss of accuracy compared to software baseline.