CSO-TFG: A Configurable Seed-Free On-the-fly Twiddle Factor Generator for NWC-Based NTT/INTT

The Number Theoretic Transform (NTT) simplifies complex polynomial multiplications into element-wise inner products, and is therefore widely adopted in various hardware accelerators. For polynomial rings, Negative Wrapped Convolution (NWC) is often used within the NTT to avoid additional zero-padding and degree expansion. However, NWC-based NTT uses nearly twice as many twiddle factors as the standard NTT, significantly increasing memory demands for constrained applications like Fully Homomorphic Encryption (FHE). Existing hardware designs primarily focus on accelerating butterfly computations in the NTT, while ignoring the memory bottleneck caused by twiddle factors. In this paper, a Configurable Seed-free On-the-fly Twiddle Factor Generator (CSO-TFG) is proposed, which dynamically generates all required twiddle factors without using any seeds and supports flexible degree configurations. The CSO-TFG is deployed on a Xilinx ZYNQ-7 FPGA, and experimental results demonstrate that it achieves a 18%-56% improvement in Throughput-Per-Area (TPA) compared to state-of-the-art works.