Design and Optimization of Power, Area, and Delay in A4-Bit SIPO Shift Register Using 90 nm CMOS Technology

Shift registers are widely utilized electronic devices for data storage and transmission. Various internal circuitry factors, including the type of technological node, design architecture, and operating power levels, influence their performance. This paper presents the design and optimization of a 4-bit Serial-In Parallel-Out (SIPO) shift register implemented in 90nm CMOS technology. The proposed design aims to enhance the performance metrics of power consumption, area, and delay, which are critical for modern digital applications. Our shift register achieves significant improvements over existing designs through advanced design techniques and optimizations. The key metrics for our design are a power consumption of 0.45 mW, an area of 110 nm x 75 nm, and a delay of 0.65 ns. These results represent improvements of approximately 18.09% in power consumption, 16% in area, and 8.45% in delay compared to a recent reference design using 90 nm CMOS technology. Our work demonstrates that through careful selection of technology nodes and design optimizations, substantial performance gains can be achieved in shift registers, making our design more suitable for energy-efficient and high-speed VLSI applications. This paper contributes to the ongoing efforts to enhance digital circuit designs, providing a more efficient and compact solution for electronic devices.