Optimized Multiplexer Architectures: A Hybrid Approach to Low-Power and High-Speed VLSI Design

A key challenge in contemporary VLSI circuit design is to ensure high speed while achieving low power consumption. Multiplexers are fundamental components of digital systems, and they have a major impact on performance and efficiency. This study examines and contrasts three distinct 4:1 multiplexer architecture: Conventional CMOS, Gate Diffusion Input (GDI), and a proposed Hybrid method that combines Pass Transistor Logic (PTL) with Transmission Gate Logic (TGL). While conventional CMOS provides a complete voltage swing and robust noise immunity, it is limited by its high transistor count and power consumption. In contrast, GDI reduces the number of transistors used and the amount of power dissipated, resulting in greater compactness and efficiency; nevertheless, it is afflicted by signal degradation and compatibility problems with standard CMOS processes. A Hybrid logic design is introduced to overcome the trade-offs associated with these techniques. As demonstrated by simulation results obtained with Cadence Virtuoso at 90nm technology, the Hybrid architecture provides a delay reduction of up to 98.9%, a power reduction of 96.6%, and a 99.96% enhancement in the power-delay product (PDP) when compared to CMOS. Additionally, it surpasses GDI in performance, with reductions of 87.1% in delay and 93.5% in power. The results of this study demonstrate that Hybrid logic is a very effective and well-balanced way to realize low-power, high-performance multiplexer circuits in advanced VLSI systems.