Design and Performance Analysis of CMOS, GDI, and PTL Logic Gates at 90nm Technology

This paper presents a comparative design and simulation analysis of fundamental logic gates using CMOS, GDI, and PTL technologies at the 90 nm technology node. Six basic gates—AND, OR, NOT, NAND, NOR, and XOR—were implemented using Cadence Virtuoso, and evaluated for power consumption, propagation delay, and transistor count through pre-layout simulations. The Cadence Spectre simulator was used to perform accurate transient analyses under a uniform test-bench, with a supply voltage of 1.2 V and a standard capacitive load. The results demonstrate that GDI-based designs achieve the highest efficiency across multiple metrics. For instance, the GDI-based AND gate used only 2 transistors and consumed 6.03 nW, compared to 6 transistors and 206.9 nW in its CMOS counterpart. Similarly, the GDI XOR gate reduced the transistor count from 14 (CMOS) to 4, while improving delay from 107.1 ps to 19.38 ps. PTL designs showed favorable delay in specific cases, such as the XOR gate achieving 12.79 ps, but often at the cost of higher power consumption (e.g., $51.38 \mu \mathrm{W}$). These findings reveal significant trade-offs among the three logic design techniques and offer design insights for developing low-power, high-speed digital circuits in nano-scale technologies.