Quadrature Clock Generator Based on Folded MCML D-Latch for Half-Rate CDR Applications

This paper presents a high-speed quadrature clock generator for half-rate Clock and Data Recovery (CDR) applications. Folded MOS Current Mode Logic (FMCML) D-latches with Clocked Forward Body Biasing (CFBB) and a Current Mode Logic (CML) buffer are used in the design, where CFBB enhances threshold voltage control, reducing propagation delay and improving speed, and the CML buffer suppresses signal distortions and stabilizes output swings. Developed using a 90 nm CMOS process and simulated in Cadence Virtuoso, the circuit operates reliably up to 11 GHz. The 5 GHz simulation exhibits proper clock generation with a consistent 90-degree phase difference between the output clocks. Transient analysis verifies the divide-by-two behavior, with outputs exhibiting halved frequencies and stable phase shifts at process corners. DC power consumption varies from 7.38 µW at 0.4 V to 303.03 µW at 1 V with stability across temperature and moderate process-corner variation. Noise performance is remarkable, with the noise density measured to be −146.59 V/√Hz at a 1 MHz offset and further reducing to approximately −157 V/√Hz at 10 GHz. Monte Carlo simulations similarly verify the reliability of the design, with average power tightly packed around 280 µWunder process variation. The results confirm that CFBB-enhanced Folded MCML latches can reliably support enabling high-speed, low-noise quadrature clock generation with promising potential for integration into half-rate CDR systems for next-generation optical and wireless communication.