Wideband and Linear Current Starved VCO with Source Degeneration and Integrated Charge Pump for ADC Front Ends

For Voltage Controlled Oscillator (VCO) based Analog-to-Digital Converter (ADC) front ends, achieving high linearity over a wide tuning range without compromising phase noise is a critical design challenge to get better performance of ADC. This paper proposes a novel five-stage current-starved ring oscillator (CSRO) with charge pump integration and diodeconnected NMOS source degeneration technique on 90nm CMOS technology for Voltage Controlled Oscillator based ADC applications. The Bandwidth is maintained where the higher frequency is sixteen times of the lower oscillation frequency for four bit ADC application. The PSS simulation confirms the frequency range, linearity for both schematic and post layout simulation. As the source degeneration resistance are replaced by cmos transistor, silicon area consumption is significantly reduced while achieving a highly reasonable linearity. The charge pump is introduced with tuned charge pump current to produce sharp transition than conventional inverter which leads to reduction of phase noise. With the tuning voltage from 0.52V to 1.6V the frequency ranges from 38Mhz to 619Mhz. The average power consumption for two terminal voltage varies from $220.9 \mu \mathrm{W}$ to $354.6 \mu \mathrm{W}$. The phase noise is achieved from -88.63 to $-87.66 \text{dBc} / \text{Hz}$, at 1MHz offset frequency. The value of dc power consumption at center frequency 329MHz is $524.4 \mu \mathrm{W}$ which leads to figure of merit of this VCO is $\mathbf{- 1 4 1. 1 5 d B c} / \mathbf{H z}$. The proposed design occupies a remarkably compact area of $292.94 \mu m^{2}$. All simulations were performed considering parasitic elements extracted from the layout and the values mentioned here is from post layout simulation.