Design of 3-2 Adder Compressor using FinFET Technology for Low Power

This work examines digital circuit design methodology for the minimization of power, delay, and power-delay product (PDP) for core circuits, such as the Multiplexer (MUX), XOR gate, and 3-2 Adder Compressor. The 3-2 Adder Compressor is an essential building block in arithmetic circuits, especially in multipliers and digital signal processors, where it minimizes the partial products count, maximizing speed and energy efficiency. We contrast traditional CMOS technology with new techniques like Pass Transistor Logic (PTL), Transmission Gate Logic (TG), and Gate Diffusion Input (GDI), as well as power-gating integration. Power-gating reduces static power by dynamically turning off idle regions, which enhances energy efficiency further. The results indicate the worst power consumption and delay characteristics of CMOS for power-efficient applications. PTL and TG improve the PDP considerably, whereas GDI is the most power-efficient technique when implemented as a stand-alone method. Powergating with header cell combined with GDI results in optimal performance with a 99% reduction in PDP from CMOS. The results demonstrate the prospect of using novel design methods for low-power VLSI systems.