Design and Verification of Low Power and High Performance Mixed Full Adder Design using LTspice 32 nm Technology

Using state-of-the-art 32nm Fin-FET technology, this research details the design and analysis of a CMOS full adder. This technique is designed to overcome the constraints of typical bulk CMOS at deep submicron nodes. A popular choice for low-power, high-performance digital circuits, Fin-FETs provide better control over short-channel effects and lower leakage currents. Utilizing Fin-FETs in both static and dynamic logic styles, the complete adder—a crucial component of arithmetic and logic circuits—is tested for performance metrics such as power consumption, latency, and power-delay product (PDP). The suggested layout takes use of the advantages of Fin-FET's double-gate structure to achieve an ideal trade-off between speed and power efficiency. The performance of the Fin-FET-based complete adder was compared to that of its bulk CMOS equivalent via the use of industry-standard tools for simulation. The architecture is well-suited for next-generation low-power and high-speed integrated circuits, as seen by the substantial increases in energy economy, switching speed, and overall scalability.