Data-Driven Static Leakage Prediction for Analog Circuits: SHAP-Based Feature Interpretation and XGBoost Optimization

As CMOS technology scales into the deep submicron regime, static leakage power has emerged as a significant contributor to total power consumption in analog circuits, particularly under aggressive process-voltage-temperature (PVT) variations. This work proposes a machine learning-based framework for accurate static leakage modeling across eight representative gate-level analog circuits. SPICE simulations based on the 22 nm PTM model are used to generate comprehensive datasets under diverse PVT conditions and input states. Four regression models—Support Vector Regression (SVR), Random Forest (RF), Extreme Gradient Boosting (XGBoost), and a Transformer-based model—are trained and evaluated using five-fold cross-validation. Among them, XGBoost demonstrates superior accuracy and robustness, achieving mean absolute percentage errors (MAPE) below 3.5% and $\mathbf{R}^{\mathbf{2}}$ values exceeding 0.98 across all gate types. SHAP-based interpretability analysis reveals that temperature and supply voltage are consistently dominant features, while input signal dependencies vary according to gate topology. The proposed approach not only outperforms traditional modeling methods in prediction accuracy but also provides physical insights into leakage behavior through interpretable feature importance analysis. This study lays the foundation for extending data-driven leakage modeling to full circuit-level applications, with future work focused on incorporating circuit topology via graph-based neural networks and validating predictions against silicon measurements.