Design of RISC V based SoC for Implantable Medical Devices

A RISC-V processor-based pacemaker system is developed to meet the stringent demands of modern medical devices, focusing on low power, real-time performance, scalability, and reliability. The architecture features a 5-stage pipelined RISC-V processor (fetch, decode, execute, memory, and write-back) for efficient parallel instruction execution, improving throughput while maintaining energy efficiency. The pacemaker continuously monitors heart rate using a comparator and classifies it as low, normal, or high. It generates adjustable-width electrical pulses during bradycardia, suppresses output during tachycardia, and allows regular pacing under normal conditions. A dedicated ALU and control unit handle real-time decision-making to ensure accurate and safe pulse regulation. Implemented in Verilog HDL, the system highlights the adaptability and precision of RISC-V architecture in critical medical applications. This design offers a robust, power-efficient, and responsive solution for implantable devices, aligning with the evolving needs of cardiac care and demonstrating the integration of domain-specific control with modern processor technology.