Machine Learning Assisted Optimization of Hybrid Full Adder based 4-bit Digital Comparator

The full adder, a crucial component of the Arithmetic Logic Unit (ALU) and a fundamental functional unit in Digital Signal Processors (DSPs) and microprocessors, is used in this study to construct a 4-bit magnitude comparator. In modern VLSI design, low-power circuit design has emerged as a crucial area of concentration. The power consumption of various 4-bit magnitude comparator systems is compared in this research. The comparator uses a design based on various full adder types, including a conventional full adder, a full adder with two XNOR gates and one multiplexer, a 2×1 multiplexer-based full adder, a NAND gate-based full adder, and an XOR-XNOR with multiplexer-based full adder, to determine whether one binary number is greater than, equal to, or less than another. A machine learning (ML) technique is incorporated to model and forecast power, delay, and area metrics under process-voltage-temperature (PVT) fluctuations to improve the performance evaluation. During the early stages of design space exploration, this prediction model helps choose the most effective design configuration. According to simulation results utilising Cadence tools in 45nm technology, the most power-delay efficient solution for low-power digital comparator applications is obtained by combining ML-driven optimisation with a 4-bit digital magnitude comparator employing complete adder architecture by providing quick and precise estimations without the need for extensive simulations, the hybrid methodology greatly enhances design decisions.