Design of a Low-Power 64-bit ALU Using Vedic Multiplication, Vinculum Encoding, and Reversible Logic on FPGA

The fusion of Vedic mathematics with reversible logic in digital system design unlocks new avenues for boosting computational efficiency while curbing energy demands. This study introduces a power-conscious vinculum-driven encoder-decoder architecture embedded within a 64-bit Vedic multiplierbased Arithmetic Logic Unit (ALU). Capitalizing on the Urdhva-Tiryagbhyam sutra and vinculum number system, the proposed model enhances throughput, trims critical path latency, and simplifies hardware overhead. Synthesized on the Artix-7 FPGA platform, the architecture showcases noteworthy energy savings, consuming only 42 mW, and registers a minimal combinational delay of 4.65 ns. Comparative analysis underscores its superiority over conventional ALU counterparts, particularly in high-speed and energy-sensitive applications. However, obstacles persist in scaling the design for broader datapaths and minimizing ancillary (garbage) outputs. Prospective research will delve into advanced refinement strategies and expanded deployment use cases. This work emphasizes the transformative potential of integrating Vedic computation techniques with reversible logic to engineer future-ready, ultra-efficient digital architectures.