Research on FPGA-Based Electronic System for Active Reset of Superconducting Qubits

Active reset of qubits is a critical step toward realizing large-scale quantum error correction(QEC) algorithms, as it enables rapid initialization of qubits to the ground state and enhances the accuracy of quantum computing. In this paper, we address the issues of existing active reset schemes that require faster feedback speeds, higher flexibility, and integration in multichannel operations. We propose a highly scalable, integrated, low-latency feedback closed-loop measurement and control system that supports local decision-making and independent judgment. The system achieves precise timing control, parameterized waveform generation, high-fidelity demodulation and decision-making computations, and rapid closed-loop feedback links. Experimental results show that the total latency of the closed-loop feedback is 243 ns, and the active reset test success rate reaches 99.5%, representing significant improvements in both efficiency and precision compared to traditional passive reset methods. Through modular design, the system supports multi-board expansion and can be adapted for concurrent reset control of large-scale qubit chips.