Fault-Tolerant Adaptive Routing in NoCs: Machine Learning Approaches for Resilient On-Chip Networks

Networks-on-Chip (NoC) have emerged as a key communication backbone for modern System-on-Chip (SoC) architectures due to their scalability, modularity, and high performance. However, as the number of integrated Intellectual Property (IP) cores increases, NoCs face significant challenges such as link failures, congestion, and routing inefficiencies, all of which can impact system reliability and performance. Fault-tolerant routing strategies have therefore become essential to maintain robust data flow and minimize downtime. Recently, machine learning (ML) techniques have shown promise in enhancing NoC resilience by enabling intelligent, adaptive routing decisions based on real-time network conditions. This paper presents a comprehensive analysis of common link faults in NoCs and explores various adaptive routing algorithms, particularly those that leverage ML for dynamic fault detection, prediction, and rerouting. Our study highlights the potential of self-learning cognitive routing methods in improving fault tolerance and maintaining efficient communication in future NoC-based systems.