Towards Efficient Privacy-Preserving Federated Learning on Edge with Reconfigurable FPGA

FPGA-based acceleration has been explored to address performance challenges in architectures incorporating federated learning (FL) and homomorphic encryption (HE). However, model updates, which involve HE, are infrequent in FL applications; thus, static allocation of FPGA resources for HE can lead to inefficiency. In response, this paper presents a work-in-progress FPGA-based FL accelerator that leverages dynamic partial reconfiguration to accelerate HE operations flexibly.