Sub 0.1-pJ/bit 14-Gb/s Receiver With Stack-Reduced Slicer Embedding One-Tap DFE for Low-Power Memory Interfaces

This brief presents a single-ended receiver (RX) with a decision feedback equalizer (DFE)-embedded and stack-reduced slicer using a DFE weight selection multiplexer (MUX). The RX employs a quarter-rate clocking architecture to reduce the on-chip clock (CK) frequency and ensure reliable operation under stringent DFE timing constraints. The slicer output is fed back to the DFE weight selection MUX integrated into the second-stage slicer, achieving a short feedback loop latency. In the proposed architecture, the number of stacked transistors in the slicer is reduced to three, thereby reducing the CK-to-Q delay and overall DFE feedback loop latency. This optimized design increases the feedback speed and alleviates DFE timing constraints, ensuring stable operation even at low supply voltages. A prototype RX was fabricated using a 65-nm CMOS process and had an area of 0.004 mm². The proposed RX achieved a measured bit error rate (BER) below $10^{-12}$ at a data rate of 14 Gb/s with an insertion loss of −12 dB and achieved a power efficiency of 0.097 pJ/bit with a supply voltage of 0.75 V.