Hardware Emulation Framework for HPC Network

In co-development model, hardware and software are developed simultaneously. Before integration, independent testing of both the components to a maximum extent, is desirable. This work proposes the technique to validate and evaluate the HPC network library without the fully functional hardware. In this work, Network Interface Card (NIC) hardware functionality is emulated in software, to test Trinetra software stack. Trinetra [1] is 200Gbps switchless torus based HPC network developed by C-DAC [2]. Trinetra implements dual data transport mechanisms tailored to message size. Latency-critical payloads are transmitted using the SFQ mode, whereas bandwidth-intensive traffic leverages the EAGER mode. The hardware functionalities required for both of these modes are emulated in software, as part of this work. Though hardware cannot be emulated completely but this approach sufficiently validates the associated software. NIC behavior is emulated in network driver. Network library interface is intentionally kept unchanged, to allow testing in its original form, as it is designed to work with actual hardware. This emulation is implemented using system memory and Linux kernel threads. Standard network benchmarks such as Intel MPI Benchmark (IMB) and OSU’s Micro-Benchmarks (OMB) are run successfully within single node, which validates this implementation and Trinetra library.