A 1.25MSPS 19bit Low-Distortion Low-Noise SAR ADC Suit for BMS Current Sampling

This paper introduces a SAR ADC suit for battery management system (BMS) current sampling. In this work, a 4-stage preamplifier with a latch structure is adopted to balance precision and speed. A distortion calibration structure based on a high-gain auxiliary operational amplifier is used to reduce the preamplifier distortion, thereby reducing the equivalent input distortion voltage of the comparator to 23.1 μV (3σ value of the normal distribution). After chip layout design and parasitic parameters extraction, the simulation results show that the designed 19 bit SAR ADC conversion rate is 1.25MSPS, when the input signal is 11.29 kHz sine wave, the dynamic signal-to-noise ratio is 94.54 dB, and the SFDR is 106.64 dB.