Reinforcement Learning-Driven CMOS 8T-SRAM Design: Optimization With Tunable Trade-Offs in Power, Delay, and Area

Driven by the continuous advancement of complementary metal-oxide semiconductor (CMOS) technology under Moore’s Law, modern microprocessors integrate over a billion transistors per chip, leading to unprecedented complexity at the transistor level. To balance power consumption, delay, and area, designers require more sophisticated optimization tools; however, traditional manual tuning and heuristic methods struggle to navigate high-dimensional process design spaces. This study presents the first reinforcement learning-driven framework based on the Soft Actor-Critic (SAC) algorithm that enables multi-objective optimization with tunable trade-offs among dynamic power, static power, delay, and area. We implemented an automated Python–LTspice closed-loop system, allowing a reinforcement learning (RL) agent trained at a 50 nm node to iteratively optimize transistor configurations for an eight-transistor static random-access memory (8T-SRAM) cell. Experimental results at the training node demonstrate reductions of up to 65% in dynamic power, 73% in static power, 39% in propagation delay, and 21% in silicon area, depending on weight settings. Additional evaluations across the 22 nm and 90 nm nodes indicate that the trained model generalizes effectively, maintaining robust optimization performance at different scales. The model significantly improves the exploration efficiency and flexibility of the optimization process compared with traditional static weighting methods, resulting in superior multi-objective balancing capabilities.