Index Randomization with Dual SRAM-PUF for Spectre Mitigation in RISC-V Branch Predictors

Spectre attacks utilize branch prediction vulnerabilities to threaten processor security. In this paper, we propose a dual SRAM-PUF branch prediction index enhancement mechanism for BOOM processors in the RISC-V ecosystem. The index generation algorithm is reconfigured to prevent the targeted manipulation of the prediction table entries by incorporating the stochastic property of physical unclonable functions. Specifically, we adopt dual SRAM-PUF arrays to realize entropy-enhanced mapping of PC values, combine position swap and XOR obfuscation to generate index sequences resistant to speculative attacks, and optimize the index allocation strategy of prediction units. Chipyard experimental validation shows that the scheme can effectively mitigate Spectre V1/V2 variant attacks, with an average reduction of branch misprediction rate of about 1.5%, and a performance loss of less than 5% in the SPEC CPU2006 benchmark test. This research provides a hardware protection scheme for RISC-V processors that balances security and performance, which has practical significance for IoT and edge computing security architectures.