Analysis of Asynchronous Chip Packaging Costs Based on IR Drop

The budget of chip packaging cannot be ignored in nowadays. With the decreasing power supply voltage of chips, advanced packaging such as flip-chip becomes an effective way to reduce the IR drop. However, it brings high packaging and additional mask costs. For large digital chips, such as SoC, if we adopt the asynchronous logic, the IR drop can be dramatically reduced, so that cheaper wire-bonding packaging becomes feasible. This paper theoretically analyzes the IR drop of asynchronous circuits, it is lower compared to synchronous circuits in both resistance, inductance, and current. Then, we implement two CPU that follows the same microarchitecture but are implemented in asynchronous and synchronous logic, respectively. By analyzing their layouts and IR drop, the results show that the asynchronous CPU effectively reduces IR drop, with a $36 \%$ smaller area, $64.10 \%$ lower power consumption, $73.30 \%$ lower maximum IR drop and $70.55 \%$ lower average IR drop compared to the synchronous one. It is showing that asynchronous circuits could reduce IR drop and then make packaging simpler.