Interrupt Caching: A Hardware-Assisted Interrupt Handling to Enhance System Responsiveness

Interrupt request (IRQ) handling is a crucial capability of modern computing systems that greatly affects system functionality and responsiveness. The necessity of OS intervention for IRQ handling is a system performance bottleneck. Existing OS solutions have no direct improvement on interrupt latency, i.e., the interval between IRQ occurrence and handler invocation. In this paper, we propose the Immediate Response by Interrupt Caching (IRIC) mechanism to reduce the interrupt latency by eliminating OS intervention. We observe that, in many workloads, there is a strong correlation among interrupts, and the currently occurring interrupts are likely to come from the same sources as the recent interrupts. We name this phenomenon interrupt locality, which refers to the tendency of interrupts to originate from the same sources in a short period. Based on this discovery, we propose a caching mechanism that stores the required information for the next IRQs inside the processor for immediate interrupt handling on a match. IRIC monitors the sequence of all IRQs using a tiny history table and loads the program counter with the handler address on a match after saving the processor state. This mechanism eliminates the need for OS intervention in handling the interrupts by caching their required information. The system protection in our general solution is guaranteed by enabling the OS to dynamically designate the list of trustful handlers in advance to take advantage of IRIC. The proposed mechanism shortens the interrupt latency by an average of 76.9% compared to the OS mechanism and decreases the standard deviation by 57.6%, which results in a significantly lower jitter and up to 2.4x speedup in workload execution. The improvements come at low hardware overhead.