Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions

This letter presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias voltage is applied using a sufficiently large resistor to further reduce parasitic capacitance. Furthermore, we also present a simple and effective method for testing very small parasitic capacitance using off-chip inverters. The test chip was fabricated using the 180-nm BCD process. The measurement results indicate that the ratio of parasitic to flying capacitance can be reduced to as low as 0.67% for 1.8-V MOS capacitors through series-connected tri-well junctions with effective biasing while only increasing a 7.7% the chip area overhead compared to the dual-well junctions.