Effects of different copper defect shapes on the behavior in TSV under thermal loading

Through-silicon vias (TSVs), which facilitate high-density signal transmission between stacked semiconductor dies, are critical vertical interconnects in three-dimensional integrated circuits (3DICs). Copper has been commonly applied as the via filling materials owing to its excellent conductivity. However, its considerable mismatch in the coefficients of thermal expansion (CTEs) with silicon can induce significant thermal stresses at the Cu-Si interface under thermal loading. Additionally, the produced defects during copper filling process would couple with thermal loading, which leads to serious reliability problems. In this study, 2-dimensional finite element analysis (2D-FEA) is employed to investigate how different copper defect shapes (keyhole-shaped, circular-shaped, long strip-shaped, thorn-shaped) affect the behavior of TSVs under thermal loading. Meanwhile, the defect location-related parameters were defined and its influence on thermal behavior was also examined. The findings provide valuable insights for improving the reliability and lifetime assessments of TSV structures, offering a foundation for advancing 3D IC manufacturing and reliability evaluations.