Silicon-based package level liquid cooling module for system on wafer (SoW)

As the development speed of Moore's Law slows down, advanced packaging has emerged as a pivotal approach to enhancing chip performance, yet the accompanying thermal management challenges have become increasingly critical. System on wafer (SoW), which integrate dense arrays of processing chips onto a silicon substrate, exhibit exceptionally high power and power density, imposing severe thermal constraints on system reliability. To address these limitations, this study innovatively develops a domain-specific thermal module employing package level liquid cooling-breakthrough beyond conventional thermal architectures. Through optimized fluidic microstructures and heat transfer pathways, the module achieves a remarkable thermal resistance reduction (measured total thermal resistance <0.04 K/W) and enables kilowatt-level cooling under a flow rate of 1.8 L/min. Experimental results demonstrate that this solution maintains the core temperature of the wafer-scale system below 78.4°C@1400W and 86.5°C@2200W. This work presents an engineering ready thermal management strategy to ensure the reliable operation of next-generation heterogeneous wafer-scale integrated systems.