A Low-Thermal-Resistance Packaging Technology in multi-chip Microsystem

With the miniaturization and integration of electronic devices, the power is continuously increasing, which brings a great challenge for the thermal management of the microsystems integrated with multi-chips. Particularly, in microsystem packaging, chips often have varying parameters, different sizes and heights. This variation inevitably creates gaps of differing sizes between the chips and the package cover plate in the longitudinal direction. These gaps impede efficient longitudinal heat transfer to the case. Consequently, heat accumulates within the device, negatively impacting its stability and long-term reliability. To transfer the heat to external efficiently, this study proposed a novel method to reduce the thermal resistance of the packaged microsystem, by in-situ deposition of the high thermal conductivity film on the cover plate, and then patterned to match the profile of the multi-chip section and electroplated to form cubic boss structures with different thicknesses, which fit the gaps and connect the chips with the cover plate. Hence, an efficient heat transfer path is established to reduce the junction-to-case thermal resistance substantially. A microsystem integrated with three chips was demonstrated and two substrates. SiC and diamond with corresponding boss structures were manufactured to verify the effect of the thermal transfer structure, and the results showed that using diamond for both the cover and heat transfer structure, the junction-to-case thermal resistance is less than 0.5 °C/W, and the maximum junction temperature of all three chips is below 78.73 °C under a total power of 45 W. We have established a low thermal resistance packaging structure for multi-chip microsystems. This structure provides an efficient method to transfer the heat accumulated within the microsystem to the external environment.