Cross-scale thermo-mechanical reliability study of voids defects in copper sintered interconnect layer

Driven by the increasing demand for high power density in power electronic devices, copper sintering technology has emerged as a critical process in advanced packaging and interconnection due to its inherently superior thermodynamic properties. However, the absence of active flux in the solder may lead to insufficient lubrication between the chip backside and the base, or issues such as high-temperature plastic deformation of the solder and inadequate wetting of the chip surface. These factors result in the formation of a certain volume fraction of randomly distributed voids within the solder layer of the chip. Such defects impede heat dissipation, thereby increasing thermal resistance. This study investigates the mechanical influence mechanism of voids defects in the solder layer of power electronic modules and systematically analyzes the effect of voids defects in the nano-copper sintered layer on thermal stress distribution and structural reliability. By designing and regulating voids models with varying types and sizes through controlled variables such as voids radius and spatial position, the research reveals that the presence of voids significantly elevates the maximum junction temperature of the chip and induces localized thermal stress in the solder layer. Additionally, as the hole radius increases, the overall temperature of the module rises, and the maximum equivalent stress of the solder layer increases. When the hole rate exceeds 20%, the upward trend of the maximum equivalent stress of the chip increases, accelerating the failure time of the power module. This discovery provides a key theoretical basis for the reliability design of power modules.